`include "define.v"

module openmips_min_sopc (
    input wire clk,
    input wire rst
);

    wire[`InstAddrBus] inst_addr;
    wire[`InstBus] inst;
    wire rom_ce;
    wire[`RegBus] bus_ram_data_ram2mips;
    wire[`RegBus] bus_ram_addr_mips2ram;
    wire[`RegBus] bus_ram_data_mips2ram;
    wire bus_ram_we_mips2ram;
    wire[3:0] bus_ram_sel_mips2ram;
    wire bus_ram_ce_mips2ram;

    wire[5:0] int;
    wire timer_int;

    assign int = {5'b00000, timer_int};

    openmips openmips0(
        .clk(clk),
        .rst(rst),

        .rom_data_i(inst),
        .rom_addr_o(inst_addr),
        .rom_ce_o(rom_ce),
        .int_i(int),
        .ram_data_i(bus_ram_data_ram2mips),
        .ram_addr_o(bus_ram_addr_mips2ram),
        .ram_we_o(bus_ram_we_mips2ram),
        .ram_sel_o(bus_ram_sel_mips2ram),
        .ram_data_o(bus_ram_data_mips2ram),
        .ram_ce_o(bus_ram_ce_mips2ram),
        .timer_int_o(timer_int)
    );

    data_ram data_ram0(
        .clk(clk),
        .ce(bus_ram_ce_mips2ram),
        .we(bus_ram_we_mips2ram),
        .addr(bus_ram_addr_mips2ram),
        .sel(bus_ram_sel_mips2ram),
        .data_i(bus_ram_data_mips2ram),
        .data_o(bus_ram_data_ram2mips)
    );

    inst_rom inst_rom0(
        .ce(rom_ce),
        .addr(inst_addr),

        .inst(inst)
    );
    
endmodule
